Circuits, such as integrated circuits (commonly referred to as “chips”) are utilized in an ever-increasing number of applications. For instance, such chips as microprocessors are commonly implemented not only in personal computers (PCs) and laptops, but are typically implemented in much smaller (and more portable) devices, such as personal digital assistants (PDAs), cellular telephones, pagers, and various other types of devices. Given the ever-increasing advances being made in the performance of chips, power consumption is increasingly becoming a concern for chip designers. For example, power consumption is becoming a serious performance limiter for high-speed microprocessors. A design objective for most microprocessor systems is to provide the highest possible peak performance for compute-intensive code, while reducing power consumption of the microprocessor system. Reduction in power consumption (at least during low performance periods) is desirable to maximize the battery life of the device, particularly when such microprocessor systems are to be implemented within portable electronic devices. Power consumption of a chip may be generally computed utilizing the following equation: P=C*V2*F, wherein P represents power consumption, C represents switching capacitance, V represents operating voltage, and F represents the clock frequency of the chip. In view of such equation, switching capacitance (C), voltage (V), and frequency (F) are all factors in determining the power consumption (P) of a chip. In many cases, the processor's clock frequency (F) is limited in order to hold the power consumption (P) of a chip below a certain level that is acceptable for use in a given system (e.g., within a desktop or portable devices).
Microprocessor chips have typically been implemented with a fixed voltage and frequency determined to prevent the chip from consuming more than a particular amount of power. Typically, in designing microprocessor chips, a designer tests the chip with software code for creating a heavy computational load on the chip in order to determine the appropriate voltage and frequency that may be implemented for the chip such that its power consumption does not exceed a particular amount when heavy computational loads are encountered by the chip. However, once implemented, such heavy computational loads may be encountered relatively seldom, with low (or no) computational load being placed on the microprocessor much of the time. Accordingly, the worst-case computational loads dictate the voltage and frequency of the chip, thereby hindering performance of the chip (e.g., because of the decreased frequency required for the worst case).
One power-saving technique attempts to reduce only the clock frequency (F) during non-compute intensive activity. This reduces power, but does not affect the total energy consumed per process. That is, a reduction in frequency (F) results in a linear reduction in the power consumed, but also results in a linear increase in task run-time, which causes the energy-per-task to remain constant. On the other hand, reducing only the voltage (V) of the processor improves its energy efficiency, but compromises its peak performance.
It has been recognized that if clock frequency (F) and supply voltage (V) are dynamically varied in response to computational load demands, then energy consumed per process can be reduced for the low computational periods, while retaining peak performance when required (i.e., for heavy computational periods). Design strategies attempting to utilize such dynamic variation of clock frequency (F) and supply voltage (V) based on computational loads are commonly referred to as dynamic voltage scaling (DVS). Examples of such DVS techniques include the SpeedStep™ technology available from Intel Corporation and the PowerNOW technology available from Advanced Micro Devices, Inc. Traditional implementations use DVS on a microprocessor under direct Operating System (OS) control. In such an implementation, one or more voltage scheduler algorithms are included in the OS of a DVS system, which are utilized to dynamically adjust the processor speed and voltage at run-time of a microprocessor. The voltage schedulers control the clock frequency (F) and supply voltage (V) of a microprocessor by writing a desired frequency (in MHz) to a coprocessor register. The voltage schedulers analyze the current and past state of the system in order to predict the future workload of the processor. For example, individual applications supply a completion deadline, and the voltage scheduler uses the applications' previous execution history to determine the number of processor cycles required and sets the clock frequency (F) accordingly.
DVS techniques traditionally utilize interval-based voltage schedulers, which periodically analyze system utilization to control the frequency and voltage. As an example, if the voltage scheduler determines that the preceding time interval was greater than 50% active, it may increase the frequency and voltage for the next time interval. Thus, the system attempts to preserve the amount of power consumed by a microprocessor by having the OS dynamically adjust the clock frequency (F) to the minimum level required by the current active processes. To adjust the clock frequency (F) to such level, the OS may cause F to either be increased or decreased. To increase F, the OS first increases the chip's operating voltage (V) to a suitable amount for supporting the desired F and then F is increased, and to decrease F to a desired level, F is first decreased to such level and then the chip's operating voltage is decreased to an amount that is sufficient for supporting the reduced F.
However, such an approach that utilizes the OS to dynamically control the voltage and frequency of a microprocessor is often problematic/undesirable. First, changing a system's OS to implement such an approach is typically very time consuming and/or costly. System administrators generally dislike upgrading their OS to improve their hardware. Additionally, the OS approach is not perfectly reliable because it has imperfect information about how much power the chip is actually consuming and what its compute needs are. Rather, the OS can only attempt to estimate/guess what is needed at the chip level. Furthermore, data necessary for the OS to intelligently estimate the power consumption and/or compute needs of a chip is typically chip specific, which results in greater difficulty in implementing/upgrading such an OS approach (because the OS implementation must be tailored to a specific chip technology that is implemented).